Wafers which are prepared from single crystal ingots of a variety of materials are used in manufacturing applications which require division of a wafer into components by cleaving along natural cleavage planes of the wafer. GaAs, GaN, AIN, and InP are representative examples of useful wafer materials for such applications; and the manufacture of lasers is a relevant example of a manufacturing application.
In the prior art, wafers, which are provided to a manufacturer, have a major Orientation Flat, termed an "OF" herein, that defines a selected set of natural cleavage planes of the wafer. In a first form, the wafers have orthogonally oriented major and minor Orientation Flats that are generated by grinding the ingot before slicing. A second form of wafer comprises a cleaved major OF and a ground minor OF.
The purpose of the minor flat is to, in combination with the major flat, uniquely identify the two plane surfaces of the wafer. For example, if, in geographic terms, the major flat is placed to face south, and the minor flat faces west, the surface of the wafer facing the viewer is the first surface. Similarly, if the major flat is placed to face south and the minor flat faces east, the surface facing the viewer is the second surface. The ability to uniquely determine the two place surfaces of a wafer is useful in all cases, and is extremely important in the cases of wafers in which both faces are polished.
Unfortunately, ground Orientation Flats are lacking in precision in their definition of natural cleavage planes. When a wafer with ground flats is to be used in an application that requires high precision in the definition of cleavage planes, the wafer must be scored and cleaved parallel to the ground OF at a distance sufficient to permit the wafer to be held during cleaving, e.g., 5 to 6 mm between the ground OF and the first cleaved plane. Thus, the portion of the wafer between the ground flat and the first line of cleavage is lost.
Because of the high cost of wafers and of component processing, any loss of wafer surface is a serious economic problem.
Furthermore, post processing of finished wafers to produce components is complicated by the presence of a reference flat. For example, where post processing includes deposition of an EPI layer, the flat causes an unwanted pattern of gas flow around the wafer, differential dissipation of heat from the wafer, and resulting mechanical deformation of the wafer. Additionally, unless the reference flat is protected during growth of an EPI layer, the layer tends to crown adjacent the flat and thus reduces the accuracy of the flat as a reference.